Welcome to the CADSTARguys Blog - Information, hints, tips and my waffle on the CADSTAR Printed Circuit Board design suite.

Please note that all names used are completely fictitious and any thing written is my own personal opinion or knowledge and not related in any way to either my employers or their customers (or Zuken).
Also this is not a replacement for proper Maintenence/support and you should read the help files before asking anything techy:).

Monday, 22 November 2010

Having trouble with components with thermal vias in heatsink pads?

Are you having trouble figuring out how to prevent your components that have a heatsink pad with thermal vias in causing errors when you run a DRC?

The type of package I am talking about is for example the QFP style with a large square middle heatsink pad that also has some vias that go through to copper features on other layers.

Unfortunately this is an oddball package that although becoming more and more popular is not (yet) fully supported in CADSTAR, in general running a DRC will bring about errors on this type of package I.E. pad to pad, unconnected pads etc.

However there is a workaround for those that do not want to see errors.
(Or more a case of building the component according to the available features in CADSTAR).

So what are we trying to achieve from this sort of component footprint?

1) A large copper pad on the board for soldering to that also provides a heatsink.

2) Some vias from the top of the large pad to another layer
    (I.E. bottom copper for GND connections)

3) A matrix of solder paste apertures.
   (A single big pad will cause both solder dragging and excess solder under the pad).

There are several issues that we need to consider.

The big pad needs a solder resist shape for it however it should not be included in the solder paste screen.
Yet if we have vias we do not want solder draining away down them so a resist dam around the via needs to be considered.

Given that the big pad solder resist will be a complete shape we will not
use the default one and instead create our own.

So first I will have a square pad (E.G. Square, 5.4mm, minimum side) and it will
have reassignments on both the top and bottom solder resist and solder paste layers of zero size. 
This is so we can control our own resist and paste shapes.

QFP with large centre pad (No resist or paste).
We cannot add vias to a component - these can only be added during routing, so instead what we do is add PTH pads instead. Here I will add a PTH pad in each corner (0.9mm pad X 0.6mm drill).

With added PTH pads (True size off for clarity, and showing temporary construction lines)
This gives us a pad with vias in, next we need to consider
both the solder resist and solder paste shapes.

For the solder resist, simply draw a square figure slightly larger than the copper pad (I.E. 0.2mm oversized).

Then  add a circular cutout in the solder resist around each PTH pad
to prevent the solder flowing down through it.

The Blue figure with cutouts is on the Top Solder Resist layer.
 That deals with the heatsinking side of it, on the bottom copper there will be 4 pads to connect to flooded copper, although you are able to simply add a square of component copper on the bottom too if you wish.

The copper pad provides the heatsink, the PTH pads provide the Vias and the Figure provides the solder resist. (You need to adjust your resist colourfiles to also include Component Outlines.)

Now to deal with the solder paste apertures.

Having a single large aperture in the solder paste screen can result in either too much solder so the pad is lifted and the other connections are poorly made also when being pasted the solder may drag and leave voids or spread where it is not wanted.
Because of these problems it is often better to provide a matrix of smaller pads to give just enough solder. (Although I have never gone as far as trying to calculate exactly how much, just adding the matrix to about 70% (ish) has always worked OK for me See Explanation).

So for this we add several SMT pads (square or rectangular - whatever fits best) with a small gap between them (approx 8-10 thou) and they do not all have to be the same size pads.
They all have Top and Bottom Solder Resist reassignments of zero size.

With added Paste pad matrix.
This now enables us to have a copper pad, via'd through with a usable solder paste matrix although we have still not dealt with the errors yet as this will have pad to pad errors for all pads on top of the large square.

So to prevent this we need to join the pads to the same net and to do this we add component copper strips between each pair of pads. As currently we can assign component copper to 2 pads at a time, we need to do this to each pair of pads in a chain until they are all connected to the large central pads.

Not forgetting that the center has 2 pads over it - so these both need connecting.

As long as the copper covers the centre of the pads and is eventually closed and filled
it will work (not forgetting the PTH pads).

With component copper - the highlighted bit joins pads 57 and 60.
This done the component can now be saved, I suggest save it as an alternative and identify that it has the PTH pads in.

When using this component you need only a single terminal on the schematic symbol for the central heatsink pad as all the pads are connected to the same net via the component copper strips so will be flooded as per your template for the bottom copper etc.

Now if you run a DRC then there will be no errors because of the smaller pads
(read vias) on the larger pad.

If you get unwanted thermal relief spokes to the paste pads then add the attribute "Pin_Routing" with the value of "Signal" to those pads to miss out any thermal relief spokes.

All this may seem quite complicated and a lot of work, however once you understand it all then you only need to do it the once and from then on it is a good usable package that enables several issues to be resolved in one go.

An addendum...de dum de dum....

Came across one of these today, where the central pad was not connected to any net.

Because it was not connected to a net, the IPC-D-356 netlist report just reports that all the pads are not connected, and that the through hole ones are shorting to the big pad.

Not a problem for us, but when at the PCB manufacturers they question it and that can cause unwanted delays.

So if you use IPC reports, make a symbol with a terminal per pin, add it to the part (as the first gate) and connect it to either GND or just connect the pins together so they have a net associated to them.


MattyLad said...

A few comments on the above:

The holes should really be approx 0.3mm-0.4mm PTH and the land only needs to be enough for plating - which if you have a larger pad either side is catered for so minimum pad size is adequate.

The holes should ideally be "filled" at board manufacture, this leaves a solid surface of the larger tab pad so there is no need of the holes in the solder resist shape.

The Solder paste pads can then be a more reasonable matrix and larger than squeezing them between holes.

When you flood copper, if you have thermal relief on pads enabled then the copper will not flood to the pad fully - so simply let it flood then place a copper shape larger than the pad+gap over the pad and connect it to the pad.
(There is another way but it involves attributes)

And all the above if a suggestion, not a definite how to as every situation is different so think about it carefully.

The CADSTAR Guy's Blog. said...

Another comment on this - for the large pad to be on both the top and the bottom - this is easily achieved when adding the large pad , Add Pad as "Through hole" rather than on "Min" and you get a pad both sides.

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